Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a storage node and a bit line and a method for manufacturing the same.
A Dynamic Random Access Memory (DRAM) includes a plurality of unit cells, each of which includes a capacitor and a transistor. The capacitor is used to temporarily store data therein. The transistor is used to transmit data between a bit line and a capacitor in correspondence with a control signal (i.e., a word line) using the electric conductivity of the semiconductor device, which changes depending on environment. The transistor has three regions including a gate, a source and a drain, where charges between the source and the drain move in response to a control signal input to the gate. The charges between the source and the drain move through a channel region in accordance with the properties and operation of the semiconductor device.
When a general transistor is formed in a semiconductor substrate, a gate is formed in the semiconductor substrate, and impurities are doped at both sides of the gate to form a source and a drain. In this case, a region between the source and the drain under the gate becomes a channel region of the transistor. The transistor, including a horizontal channel region, occupies a semiconductor substrate having a predetermined area. Reducing the overall area of a complicated semiconductor memory apparatus is difficult due to a plurality of transistors contained in the semiconductor device.
If the overall area of the semiconductor memory apparatus is reduced, the number of semiconductor memory devices capable of being acquired from each wafer is increased, resulting in increased productivity. A variety of methods have been proposed to reduce the overall area of the semiconductor memory device. For example, in one such method, a recess is formed in a substrate and a gate is formed in the recess such that a channel region is formed along a curved surface of the recess, instead of using a conventional planar gate having a horizontal channel region. With the development of the above recess gate, another method for burying the entirety of the gate in the recess to form a buried gate has also been proposed.
In the buried gate structure, a bit line contact and a storage node contact are formed by a damascene technique. Through application of the damascene technique, only an isolation film as high as a hard mask critical dimension (CD) remains between two storage node contacts. One storage node is formed between the storage node contact coupled to the storage node and the bit line hard mask. If the distance between two storage node contacts is gradually reduced as described above, a bridge failure unavoidably occurs between a storage node and a neighboring storage node contact even if there is a slight misalignment.
In a 8F2 unit cell configuration (F is a minimum pattern size of a given device structure) or larger, the distance between a storage node and a neighboring storage node contact plug is more than 1F, typically 3F. Thus, even if a storage node is formed to be slightly shifted in one direction due to misalignment, the risk that the storage node and the neighboring storage node contact plug come into contact, thus causing an electrical short, is not great.
In contrast, in a device employing a 6F2 unit cell configuration or below, the distance between a storage node and a neighboring storage node contact plug is 1F or less. Thus, even a slight misalignment may cause an electrical short between the storage node and the neighboring storage node contact plug.